No self-introduction
Loading
Profile
Follow
codes (2)
Tiny Microcontroller for FPGAs A
no vote
Application background Leros - is a tiny microcontroller that is optimized for AbstractLow-cost FPGAs. Leros is designed with a balanced logic currentOn-chip memory relation. The design goal is a microcontroller toCan be clocked in about half of the speed a pipelined on-chip thatAnd consuming less than logic 300 cells. memoryArchitecture which, follows from the design goals is, a The16-bit accumulator processor. An implementation of pipelinedNeeds at least one on-chip memory block and a few hundred LerosCells. logicApplication areas of Leros are twofold: First it, can be used TheAn intelligent peripheral device for auxiliary functions in an asBased system-on-chip design. Second the, very small size FPGALeros makes it an attractive softcore for many-core research ofLow-cost FPGAs. with Key Technology Smallest; core is comparable to Leros and can be implemented The Less than LCs. 700 It is a sequential implementation and inInstruction takes at
yijingjing 0 0
1
8051 FPGA Verilog Core complete
no vote
Application background Separation of program and data memory LogicalAll 8051 have specific memory organization they, have separate address spaces devicesProgram and (ROM) Data Memory. (RAM) This logical separation of Memory is forBecause it allows the Data Memory to be accessed by 8-bit addresses useful, can whichBe more quickly stored and manipulated by an 8-bit CPU. Of course obviously, l6-bit theMemory addresses can still be generated with the DPTR register. DataMemory ProgramMemory can only be read not, written to. The address space for core 8051 is 16- ProgramBit, there is maximum of 64K bytes of Program Memory. Up to Kbytes 4 of Program soCan be on chip internal, Program Memory of the core. 8051 For access to MemoryProgram Memory is used signal PSEN external (Store Enable Program).Memory DataMemory is on a separate address space than Program Memory. For external Data DataAccesses the CPU generates read and write signals RD and WR Memory, needed. asMemory archi
yijingjing 3 0
1
No more~
Follows0
Fans0