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SDRAM VERILOG
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The always clause above illustrates the other type of method of use, i.e. it executes whenever any of the entities in the list (the b or e ) changes. When one of these changes, a is immediately assigned a new value, and due to the blocking assignment, b is assigned a new value afterward (taking into account the new value of a ). After a delay of 5 time units, c is assigned the value of b and the value of c ^ e is tucked away in an invisible store. Then after 6 more time units, d is assigned the value that was tucked away. Signals that are driven from within a process (an initial or always block) must be of type reg . Signals that are driven from outside a process must be of type wire . The keyword reg does not necessarily imply a hardware register.
nediljko
2016-08-23
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