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RS decoder
no vote
Reed-Solomon Encoder and Decoder are commonly used in data transmission and storage applications, such as broadcast equipment, wireless LANs, cable modems, xDSL, satellite communications, microwave networks, and digital TV
thuanbk2010 3 0
1
Verilog Jpeg Encoder
4.1
This core takes as an input the red, green, and blue pixel values, like from a tiff image file, and creates the JPEG bit stream necessary to build a jpeg image. The core was written in generic, regular Verilog code that can be targeted to any FPGA. The core does not rely on any proprietary IP cores, instead all of the functions required to implement the JPEG encoder are written in Verilog and the code is entirely self-contained. This core has been simulated on many raw images with different quantification and Huffman tables.
thuanbk2010 7 0
1
Design module Bluetooth by verilog
4.0
The Bluetooth is a standard protocol for wireless connection between devices such as cell phones, PDAs, PCs and any other device. The main objective for this standard is to provide a royalty free standard for such wireless protocol. The objective of this project is to build an opensource free bluetooth baseband controller, LMP, HCI and higher layers software stacks
thuanbk2010 0 0
1
datasheet rosetta
no vote
The ROSETTA Configurable Dot Matrix Display Controller core provides a modular
expandable interface for any dimension displays build from LEDs dot matrix structures.
This core can be configured for synthesis and P&R with any number of DM LEDs slices.
These slices can be arranged in any number to form linear or plane screens.
In designs with a big number of slices, the number of pins required for the
implementation device selected could collapse. In order to overcome this inconvenience,
the output bus has a multiplexed structure, and the size of the display can be expanded
using external buffer devices.
In limited size implementations, the display columns could optionally be serviced using
the controller chip drivers, if a device with enough driving capability is used. On the
other hand, the row lines will always need some external buffering
thuanbk2010 0 0
1
code verilog cordic
no vote
This is a project about VLSI design.Topic is design for CORDIC (for CO ordinate thuanbk2010 2016-08-23
thuanbk2010 0 0
1
Digital Clock Project-FPGA
4.0
This is a FPGA based Digital Clock Project. It has the capability to display time,set time and reset it. It basically uses 2 mod 60 counters and a mod 24 counter. Each time the seconds counter reaches 60, it is reset and the minute counter is incremented. Every time the minute counter reaches 60, it is reset and the hour counter is incremented. Every time the hour counter reaches 24, it is reset. A clock pulse of 100khz if given to the FPGA which is converted to 1hz using clock division technique. This 1hz clock pulse is used to drive the seconds counter and this is how this project works. It is working and synthesizable i.e. downloadable onto the FPGA
thuanbk2010 0 0
1
Digital Alarm Clock FPGA
4.5
The aim this project is to implement the functionality of a digital alarm clock on a FPGA. As soon as the FPGA is switched on, the clock starts. The alarm can be set using the dip-switches provided on the FPGA board. This is indicated through the LEDs of the corresponding dip switch. The counter keeps rolling and as soon as the alarm goes off, a buzzer like sound is magnified via a speaker. This project is full.Enjoy it !
thuanbk2010 3 0
1
code verilog cordic core
4.0
A 100% behavioral implementation of a cordic core. The core is highly configurable through `defines. A testbench is included. See the included manual for details
thuanbk2010 0 0
1
code verilog for cordic
4.5
This is a project about VLSI design.Topic is design for CORDIC (for CO ordinate thuanbk2010 2016-08-23
thuanbk2010 4 0
1
Code verilog for motion compensated prediction blo
no vote
This is a project about VLSI design.Topic
is design for motion compensated prediction block in compressed
video.Project consisted Code RTL,Code Testbench.
Project
use software of synopsys for example: Design Compiler (Synthesis),IC Compiler (Layout) ...
thuanbk2010 2016-08-23
thuanbk2010 0 0
1
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