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vhdl code for latch_ff_comb for d_comb ckt in vhdl
4.0
library ieee;
use ieee.std_logic_1164.all;
entity d_comb is
port( enable:in std_logic;
d:in std_logic;
q:out std_logic);
end d_comb;
architecture rtl of d_comb is
begin
process(enable,d)
begin
if(enable='1')then
q<=d;
else
q<='0';
end if;
end process;
end rtl;
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