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FPGA'for' cycle
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Written in the Verilog language for circulation and used to verify whether in the FPGA can writing a for loop in c, it turned out although the emulation to get the right result, but in real engineering are not compile-time takes 24 hours to complete, so I chose another method to loop through, after all, the FPGA is parallel, and c is the serial.
xujieCodeForge457612 0 0
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LineBuffer simulation
4.0
Verilog in writing, called IP cores enable project development easier and faster, for starters, called IP core abstractions, through a specific simple example can give you a clear understanding of IP cores is called learning Verilog is helpful.
xujieCodeForge457612 0 0
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FIFO IP core calls and simulation
4.0
FIFO IP calls in our project can shorten design cycles, eliminates the complex process of writing code, but also eliminates the complexity of the debugger and the complexity of the code. This little simple FIFO IP core called to make it clear for everyone to understand FIFO principle and method called IP core.
xujieCodeForge457612 0 0
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