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aynchronous fifo project
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First-In
First-Out (FIFO) memory structures are widely used to buffer the transfer of
data between processing blocks. High performance and high complexity digital
systems increasingly are required to transfer data between modules of differing
and even unrelated clock frequencies. The dual-clock FIFO is a more complex
function that can provide high-speed data buffering for asynchronous clock
domain applications. The proposed design utilizes an efficient memory array
structure and can operate in applications where multiple clock cycles of
latency exist. It also includes a configurable synchronization circuit that
synchronizes asynchronous signals within the FIFO.
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