VHDL code for Adder / Subtractor
4.0
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY adder IS
PORT(Cin : IN STD_LOGIC;
Carry : IN STD_LOGIC;
X,Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
Cout,A,B,C,D : OUT STD_LOGIC;
rseg : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END adder;
ARCHITECTURE Behavior OF adder IS
SIGNAL Sum: STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
PROCESS (Cin, X,Y)
BEGIN
IF Cin ='0' THEN
Sum<= ('0' & X)+Y+Carry;
ELSE
Sum<= ('0' & X)-Y;
END I