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ADPLL behavior model
4.0
The attached files contain the behavior model of ADPLL.
The 6 bits TDC is used. A fast clock is used to count the the timing difference between the input reference clock and feedback clock.
The TDC resolution is higher if the fast clock is faster.
The digital loop filter produces 14 digital control bits to control the frequency of DCO.
A 14 bit DAC is used for convenience to control the DCO by the means like controlling VCO.
A 4330 divider is used in the attached file.
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