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vhdl code for different adders
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A multiplier is one of the key hardware blocks in most digital and high
performance systems such as FIR filters, digital signal processors and
microprocessors etc. With advances in technology, many researchers have tried
and are trying to design multipliers which offer either of the following- high
speed, low power consumption, regularity of layout and hence less area or even
combination of them in multiplier. Thus making them suitable for various high
speed, low power, and compact VLSI implementations. However area and speed are
two conflicting constraints. So improving speed results always in larger areas.
So here we try to find out the best trade off solution among the both of them.
Generally as we know multiplication goes in two basic steps. Partial product
and then addition. Hence in this project we have first tried to design different
adders and compare their speed and complexity of circuit i.e. the area
occu
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