No self-introduction
Loading
Profile
Follow
codes (1)
VHDL code for counter
4.0
Here is the code for counter in VHDL.
--signal slow_clk : std_logic := '0';
--signal clk_divider : std_logic_vector(23 downto 0) := x"000000";
-- Clock divider can be changed to suit application.
-- Clock (clk) is normally 50 MHz, so each clock cycle
-- is 20 ns. A clock divider of 'n' bits will make 1
-- slow_clk cycle equal 2^n clk cycles.
-- Process that makes slow clock go high only when MSB of
-- clk_divider goes high.
--clk_division : process (clk, clk_divider)
BugraYalituna 0 0
1
No more~
Follows0
Fans0