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system verilog program
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tlm communication betwwen two components producer and consumer. communication provided by ports and exports. code can be written in uvm.
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uvm book cook
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universal verification methodology book version 1.0 which is industrial standard. verification codes can be wrritten in uvm
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fifo environment in sv
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Asynchronous fifo has been verified by using system verilog . 100 % functional coverage & code coverage has been provided. environment has been created different test cases are written to meet the requirements.
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i2c protocol
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The I? C is generally referred to as & quot; two wireinterfaces & quot;. The thisI? C interface will create communication between master and slave devices. The interface will read the master's command and send the corresponding response to the master. The design of ourinterface, including read and write operations, will be able to communicate and master through I2C slave.
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