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A Hardware and Software Monitor for High-Level Sys
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Today's system on chip (SOC) verification occurs at a low level of abstraction, usually at the register transfer level (RTL). With the complexity of SoC design, it is more and more important to move to a higher level of abstraction for verification. Hardware / Software Co simulation is the direction of this step, but because the wrong processor is not enough model and low hardware simulation speed. System level monitoring, usually used for event based software debugging, provides information about task scheduling events, inter task communication and synchronization, semaphore / resource, I / O interrupt, etc. at present, mamon1 can monitor two monitoring logic levels and system level
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