No self-introduction
Loading
Profile
Follow
codes (3)
AMBA_ AHB（amba AHB coding in verilog HDL and integr
no vote
AMBA_ AHB（amba AHB coding in verilog HDL and integrating with AHB to AXI Brigde ）
redleaf 0 0
1
AXI_ MIG (ISE generated MIG of Axi interface, memory controller, language: Verilog ISE generator)
no vote
AXI_ MIG (ISE generated Axi interface MIG, memory controller, Language Verilog)
redleaf 0 0
1
AXI slave verilog code
4.1
Wrote AXI slaver Verilog code, hope to give you some inspiration
redleaf 16 0
1
No more~
Follows0
Fans0