A cyclic redundancy check (CRC) is an error-detection code commonly used in digital systems,
e.g., in network and storage devices to detect accidental changes to raw data and also in DFT
(Design for Testability) circuits for test compaction. Blocks of data entering these systems get a
short check value attached, based on the remainder of a polynomial division of their contents; on
retrieval the calculation is repeated, and proper action can be taken against presumed data
corruption, or faulty result when the check values do not match.
In this lab, we need to design parameterized CRC module (in Verilog) to generate the fixed-
length check value