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i2c core including master and slave
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I2C-HS Master/Slave Bus Controller Core The I2C-HS core implements a serial interface that meets the Philips I2C Bus® specification version 2.1. It is compliant with the PVCI (Peripheral Virtual Component Interface) standard which is an open standard for SoC On-Chip Bus. The I2C-HS is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous ...
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