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I2C protocol on FPGA verilog code
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This is a slave protocol for FPGA EEPROM on a 512Kb EEPROM, it should be working for Nexys4 FPGA. The slave protocol uses a Tri-State buffer to control the SDA and SCL inouts of the FPGA, you should connect the pins of the EEPROM to the I/O of the Nexys, therefore try to upload this trough Xilinx and then try it. The idea of the code is to help people to move forward on their projects or works, this code would be useful to people really stuck on EEPROM i2c programming
yunta23 0 0
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7 segments display on Nexys 4
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This is an easy way to create a verilog module for 7 segments purpose, is very easy to read and it can be tested on your nexys 4 FPGA.
yunta23 0 0
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