Home » Source Code » Traffic light controller

Traffic light controller

ARUN
2013-10-30 23:42:42
The author
View(s):
Download(s): 0
Point (s): 1 
Category Category:
vhdlvhdl VHDLVHDL

Description

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_unsigned.all;

entity traffic is

port (clk: in STD_LOGIC;

clr: in STD_LOGIC;

lights: out STD_LOGIC_VECTOR(5 downto 0));

end traffic;

architecture traffic of traffic is

type state_type is (s0, s1, s2, s3, s4, s5);

signal state: state_type;

signal count: STD_LOGIC_VECTOR(3 downto 0);

constant SEC5: STD_LOGIC_VECTOR(3 downto 0) := "1111";

constant SEC1: STD_LOGIC_VECTOR(3 downto 0) := "0011";

begin

process(clk, clr)

begin

if clr = '1' then

state <= s0;

count <= X"0";

elsif clk'event and clk = '1' then

case state is

when s0 =>

if count < SEC5 then

state <= s0;

count <= count + 1;

else

state <= s1;

count <= X"0";

end if;

when s1 =>

if count < SEC1 then

state <= s1;

count <= count + 1;

else

state <= s2;

count <= X"0";

end if;

when s2 =>

if count < SEC1 then

state <= s3;

count <= count + 1;

else

state <= s3;

count <= X"0";

end if;

when s3 =>

if count < SEC5 then

state <= s3;

count <= count + 1;

else

state <= s4;

count <= X"0";

end if;

when s4 =>

if count < SEC1 then

state <= s4;

count <= count + 1;

else

state <= s5;

count <= X"0";

end if;

when s5 =>

if count < SEC1 then

state <= s5;

count <= count + 1;

else

state <= s0;

count <= X"0";

end if;

when others =>

state <= s0;

end case;

end if;

end process;

C2: process(state)

begin

case state is

when s0 => lights <= "100001";

when s1 => lights <= "100010";

when s2 => lights <= "100100";

when s3 => lights <= "001100";

when s4 => lights <= "010100";

when s5 => lights <= "100100";

when others => lights <= "100001";

end case;

end process;

end traffic;

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_unsigned.all;

entity clkdiv is

port(

mclk : in STD_LOGIC;

clr : in STD_LOGIC;

clk190 : out STD_LOGIC;

clk3 : out STD_LOGIC

);

end clkdiv;

architecture clkdiv of clkdiv is

signal q:STD_LOGIC_VECTOR(24 downto 0);

begin

 

process(mclk, clr)

begin

if clr = '1' then

q <= X"000000" & '0';

elsif mclk'event and mclk='1' then

q <= q + 1;

end if;

end process;

clk3 <= q(24); -- 3 Hz

clk190 <= q(18); -- 190 H

end clkdiv;

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_unsigned.all;

 

entity traffic_lights_top is

port(

clk : in STD_LOGIC;

btn : in STD_LOGIC_VECTOR(3 downto 3);

ld : out STD_LOGIC_VECTOR(7 downto 2)

);

end traffic_lights_top;

architecture traffic_lights_top of traffic_lights_top is

component clkdiv is

port(

mclk : in STD_LOGIC;

clr : in STD_LOGIC;

clk190 : out STD_LOGIC;

clk3 : out STD_LOGIC

);

end component;

component traffic is

port (clk: in STD_LOGIC;

clr: in STD_LOGIC;

lights: out STD_LOGIC_VECTOR(5 downto 0));

end component;

signal clr, clk3: STD_LOGIC;

begin

clr <= btn(3);

U1: clkdiv

port map (

mclk=>clk,

clr=>clr,

clk3=>clk3

);

U2: traffic

port map (

clk=>clk3,

clr=>clr,

lights=>ld

);

end traffic_lights_top;

 

 

Sponsored links

File list

Tips: You can preview the content of files by clicking file names^_^
Name Size Date
tlc.docx13.44 kB2013-10-24 19:42
...
Sponsored links

Comments

(Add your comment, get 0.1 Point)
Minimum:15 words, Maximum:160 words
  • 1
  • Page 1
  • Total 1

Traffic light controller (10.86 kB)

Need 1 Point(s)
Your Point (s)

Your Point isn't enough.

Get 22 Point immediately by PayPal

Point will be added to your account automatically after the transaction.

More(Debit card / Credit card / PayPal Credit / Online Banking)

Submit your source codes. Get more Points

LOGIN

Don't have an account? Register now
Need any help?
Mail to: support@codeforge.com

切换到中文版?

CodeForge Chinese Version
CodeForge English Version

Where are you going?

^_^"Oops ...

Sorry!This guy is mysterious, its blog hasn't been opened, try another, please!
OK

Warm tip!

CodeForge to FavoriteFavorite by Ctrl+D