Floating Multiplication in Verilog FPGA
2016-08-23
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The design of digital multiplier has received increasing attention as it becomes an indispensable part of
modern computer. The paper introduces the design of a floating multiplier based on the compensate
shifting in the hardware description language. The design can fulfill full function and is of better flexibility,
with its theory based on floating calculating and compensate shift multiplication. The paper describes the
environments for developing and testing, and a function simulation is included.
verilog
乘法
浮点
VerilogFPGA
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