1 bit adder module register transfer level and gat
2016-08-23
0 0 0
no vote
Other
Earn points
This simple project gives an example of how to write a simple 1 bit adder and test it before synthesis and after synthesis with design compiler.
Register transfer level is the code that you write and its simulation show ideal timing diagrams.
Gate level is the code after synthesis and Design Compiler and contains real timing diagrams and simulation.
verilog
模拟
模块
注册
加法器
转让
Related Source Codes
AXI Host Slave Function Model
0
0
no vote
Axi slave to fifo code
0
0
no vote
DMA Controller Based on AHB
0
0
no vote
Verilog implementation of ldpc code
0
0
no vote
Minimum sum decoding
0
0
no vote
No comment