async fifo
2016-08-23
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`timescale 1ns/1ps
13
14 module aFifo
15 #(parameter DATA_WIDTH = 8,
16 ADDRESS_WIDTH = 4,
17 FIFO_DEPTH = (1 << ADDRESS_WIDTH))
18 //Reading port
19 (output reg [DATA_WIDTH-1:0] Data_out,
20 output reg Empty_out,
21 input wire &nb
13
14 module aFifo
15 #(parameter DATA_WIDTH = 8,
16 ADDRESS_WIDTH = 4,
17 FIFO_DEPTH = (1 << ADDRESS_WIDTH))
18 //Reading port
19 (output reg [DATA_WIDTH-1:0] Data_out,
20 output reg Empty_out,
21 input wire &nb
verilog
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