Eye graphic design Stimulator
2016-08-23
0 0 0
no vote
Other
Earn points
Complete screen half screen black and white chequered, red and green-screen half screen vertical bar grille, blue-green screen half screen stripped six cycle transitions between graphics format of the grating, realized by FPGA VGA display. Design of the top-level file requires several modules: PLL module frequency timing module, timing control module and display module. For each module completed realization and simulation using VHDL language, then generate the module on top of the block file. PLL module Breadboard hardware is the role of 50MHz transformation for VGA800*600 40MHz clock timing module scheduled for 5 seconds every 5 seconds to convert a graphic display; timing control module for scanning, or blanking, enables to display correctly; display module is displayed. Correct wiring of each module, define a PIN and after the simulation, can be downloaded to the FPGA, connect the monitor to display, six graphics conversion programme every 5 seconds, c
vhdl
设计
图形
Related Source Codes
Lubansuo Drawing
0
0
no vote
EE247 Analysis and design of analog-to-digital int
0
0
no vote
Java multi instance mode
0
0
no vote
Java singleton mode
0
0
no vote
Beiyou digital experiment parking lot
0
0
no vote
No comment