A High-Throughput Low-Cost Implementation for AES-
2016-08-23
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In a real solid-state disk project, we presente a high throughput and low cost solution to implement data security using AES-128 and Counter mode encryption algorithm. The AES-128 encryption flow has five module including SubBytes, ShiftRows, MixColumns, AddRoundKeys and KeyExpansion. Among these module, the SubBytes module is far more complex architectures, which implements an add, multplier, inverse computation in galois filed (GF(2)). We implemented cryptographic circuit in Spartan3E field programmable gate array (FPGA) platform. The final test results show that the presented implementation has a high-throughput up to 1.7Gbps at the low occupation of FPGA resource.
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