mii_to_rmii
2016-08-23
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The LogiCORE ™ IP Media Indepenent Interface (MII)to Reduced Media Independent (RMII) design providesthe RMII between RMII-compliant ethernet physicalmedia devices (PHY) and Xilinx 10/100 Mb/s ethernetcores such as the XPS LL TEMAC and XPS EthernetLite. These cores provide the traditional MII thatrequires sixteen signals to communicate with anethernet PHY. The MII to RMII core accepts the sixteensignal MII interface and provides a six or seven signalinterface to an RMII compliant PHY. Additionally, afixed 50 MHz reference clock synchronizes the MII toRMII core with both interfaces. The 50 MHz referenceclock may be provided by a source external to the hostFPGA, or generated within the host FPGA. The MII toRMII core follows the specification defined by the RMIIConsortium (version 1.0).
miitormii
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