AXI slave Verilog implementation of agreements
2016-08-23
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Axi (Advanced extensible interface) is a bus protocol, which is the most important part of AMBA (advanced microcontroller bus architecture) 3.0 protocol proposed by arm company. It is an on-chip bus with high performance, high bandwidth and low latency. Its address / control and data phase are separated, which supports the data transmission of misalignment. At the same time, in the burst transmission, only the first address is needed, and the read-write data channel is separated at the same time. It also supports the out standing transmission access and out of order access, and it is easier to achieve timing convergence. Axi is a new high performance protocol in AMBA. Axi technology enriches the existing AMBA standards to meet ultra-high performance and complex requirements
verilog
协议
slave
实现
AXI
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