Pipelined FFT/IFFT 64 points processor
2016-08-23
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64 -point radix-8 FFT.
Forward and inverse FFT.
Pipelined mode operation, each result is outputted in one clock cycle, the latent delay from
input to output is equal to 163 clock cycles, simultaneous loading/downloading supported.
Input data, output data, and coefficient widths are parametrizable in range 8 to 16.
Two and three data buffers are selected.
FFT for 10 bit data and coefficient width is calculated on Xilinx XC4SX25-12 FPGA at
250 MHz clock cycle, and on Xilinx XC5SX25-12 FPGA at 300 MHz clock cycle,
respectively.
Forward and inverse FFT.
Pipelined mode operation, each result is outputted in one clock cycle, the latent delay from
input to output is equal to 163 clock cycles, simultaneous loading/downloading supported.
Input data, output data, and coefficient widths are parametrizable in range 8 to 16.
Two and three data buffers are selected.
FFT for 10 bit data and coefficient width is calculated on Xilinx XC4SX25-12 FPGA at
250 MHz clock cycle, and on Xilinx XC5SX25-12 FPGA at 300 MHz clock cycle,
respectively.
verilog
流水线
fftifft
处理器
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