SPI interface design
2016-08-23
2 0 0
no vote
Other
Earn points
SPI interface circuit of the main mode design: (1) frequency 100M, adjustable output clock frequencies: master clock frequency 2/4/8/32/64, and (2) has an active transceiver function; (3) 16bit send, receive data as a unit, (4) use SMIC craft smic18mm_1P6M completed the design, (5) complete all processes: design specification document, module design, code, functional simulation , Constraint and synthesis, place and route, timing simulation, verification, etc.
verilog
spi
设计
接口
Related Source Codes
TMS320F28335 DSP transmits data to EEPROM through
0
0
no vote
AXI Host Slave Function Model
0
0
no vote
Axi slave to fifo code
0
0
no vote
DMA Controller Based on AHB
0
0
no vote
Verilog implementation of ldpc code
0
0
no vote
No comment