UART Verilog
2016-08-23
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Zip file contains the top-level files and test files. Finished sending and receiving. Delivery module and receiver modules are described in the file at the top level. To define several different communication speed. Send and receive rules are 10 bit is sent at a time. Entirely on serial communication principles. Guarantee that each bit can guarantee enough time.
verilog
UARTVerilog
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