111 classic instances of Verilog
2016-08-23
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Verilog HDL is a kind of hardware description language, which is used to model digital system at various abstract design levels from algorithm level, structure level, gate level to switch level. The complexity of digital system object to be modeled can be between switch level circuit (such as PMOS / NMOS), simple gate (such as library unit description) and complete complex electronic digital system (such as CPU)
verilog
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AXI Host Slave Function Model
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Verilog implementation of ldpc code
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Minimum sum decoding
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