Tiny Microcontroller for FPGAs A
2016-08-23
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Application background
Leros - is a tiny microcontroller that is optimized for AbstractLow-cost FPGAs. Leros is designed with a balanced logic currentOn-chip memory relation. The design goal is a microcontroller toCan be clocked in about half of the speed a pipelined on-chip thatAnd consuming less than logic 300 cells. memoryArchitecture which, follows from the design goals is, a The16-bit accumulator processor. An implementation of pipelinedNeeds at least one on-chip memory block and a few hundred LerosCells. logicApplication areas of Leros are twofold: First it, can be used TheAn intelligent peripheral device for auxiliary functions in an asBased system-on-chip design. Second the, very small size FPGALeros makes it an attractive softcore for many-core research ofLow-cost FPGAs. withKey Technology
Smallest; core is comparable to Leros and can be implemented The Less than LCs. 700 It is a sequential implementation and inInstruction takes atverilog
ATinyMicrocontrollerforFPGAs
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