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Verilog LCD code

leo10101068a
2015-09-15 11:26:45
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VerilogVerilog VHDLVHDL

Description

Application background

This code can be used in the II Verilog VHDL Quartus to write the LCD module and can be used in the DE2 simulation experiments!!

Key Technology

This code can help beginners to use the LCD display on the FPGA display text and then make appropriate changes can be used in their own place!!
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File list

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Name Size Date
LCD.(0).cnf.cdb4.72 kB11-09-15|17:10
LCD.(0).cnf.hdb1.79 kB11-09-15|17:10
LCD.asm.qmsg2.32 kB11-09-15|17:16
LCD.asm.rdb1.45 kB11-09-15|17:16
LCD.asm_labs.ddb24.04 kB11-09-15|17:16
LCD.cbx.xml85.00 B11-09-15|17:16
LCD.cmp.bpm638.00 B11-09-15|17:16
LCD.cmp.cdb11.06 kB11-09-15|17:16
LCD.cmp.hdb11.26 kB11-09-15|17:16
LCD.cmp.idb2.01 kB11-09-15|17:16
LCD.cmp.kpt214.00 B11-09-15|17:16
LCD.cmp.logdb4.00 B11-09-15|17:16
LCD.cmp.rdb23.43 kB11-09-15|17:16
LCD.cmp0.ddb63.10 kB11-09-15|17:16
LCD.cmp1.ddb63.03 kB11-09-15|17:16
LCD.cmp_merge.kpt220.00 B11-09-15|17:16
LCD.db_info152.00 B11-09-15|17:16
LCD.fit.qmsg21.92 kB11-09-15|17:16
LCD.hier_info863.00 B11-09-15|17:16
LCD.hif533.00 B11-09-15|17:16
LCD.ipinfo175.00 B11-09-15|17:16
LCD.lpc.html372.00 B11-09-15|17:16
LCD.lpc.rdb411.00 B11-09-15|17:16
LCD.lpc.txt1.04 kB11-09-15|17:16
LCD.map.bpm609.00 B11-09-15|17:16
LCD.map.cdb4.28 kB11-09-15|17:16
LCD.map.hdb10.64 kB11-09-15|17:16
LCD.map.kpt2.32 kB11-09-15|17:16
LCD.map.logdb4.00 B11-09-15|17:16
LCD.map.qmsg6.14 kB11-09-15|17:16
LCD.map.rdb1.28 kB11-09-15|17:16
LCD.map_bb.cdb1.08 kB11-09-15|17:16
LCD.map_bb.hdb8.26 kB11-09-15|17:16
LCD.map_bb.logdb4.00 B11-09-15|17:16
LCD.pplq.rdb243.00 B11-09-15|17:17
LCD.pre_map.cdb5.22 kB11-09-15|17:16
LCD.pre_map.hdb10.23 kB11-09-15|17:16
LCD.qns10.00 B11-09-15|17:17
LCD.root_partition.map.reg_db.cdb528.00 B11-09-15|17:16
LCD.routing.rdb12.52 kB11-09-15|17:16
LCD.rtlv.hdb10.07 kB11-09-15|17:16
LCD.rtlv_sg.cdb4.77 kB11-09-15|17:16
LCD.rtlv_sg_swap.cdb193.00 B11-09-15|17:16
LCD.sas10.00 B11-09-15|17:17
LCD.sgdiff.cdb4.10 kB11-09-15|17:16
LCD.sgdiff.hdb10.45 kB11-09-15|17:16
LCD.sld_design_entry.sci213.00 B11-09-15|17:26
LCD.sld_design_entry_dsc.sci213.00 B11-09-15|17:16
LCD.smart_action.txt6.00 B11-09-15|17:16
LCD.smp_dump.txt1.08 kB11-09-15|17:16
LCD.sta.qmsg11.30 kB11-09-15|17:16
LCD.sta.rdb16.78 kB11-09-15|17:16
LCD.sta_cmp.6_slow.tdb9.77 kB11-09-15|17:16
LCD.syn_hier_info0.00 B11-09-15|17:16
LCD.tis_db_list.ddb189.00 B11-09-15|17:16
LCD.vpr.ammdb322.00 B11-09-15|17:16
logic_util_heursitic.dat4.13 kB11-09-15|17:16
prev_cmp_LCD.qmsg42.30 kB11-09-15|17:14
LCD.db_info152.00 B11-09-15|17:10
LCD.root_partition.cmp.ammdb311.00 B11-09-15|17:16
LCD.root_partition.cmp.cdb5.60 kB11-09-15|17:16
LCD.root_partition.cmp.dfp33.00 B11-09-15|17:16
LCD.root_partition.cmp.hdb10.97 kB11-09-15|17:16
LCD.root_partition.cmp.kpt216.00 B11-09-15|17:16
LCD.root_partition.cmp.logdb4.00 B11-09-15|17:16
LCD.root_partition.cmp.rcfdb4.27 kB11-09-15|17:16
LCD.root_partition.map.cdb4.24 kB11-09-15|17:16
LCD.root_partition.map.dpi811.00 B11-09-15|17:16
LCD.root_partition.map.hbdb.cdb631.00 B11-09-15|17:16
LCD.root_partition.map.hbdb.hb_info46.00 B11-09-15|17:16
LCD.root_partition.map.hbdb.hdb10.36 kB11-09-15|17:16
LCD.root_partition.map.hbdb.sig32.00 B11-09-15|17:16
LCD.root_partition.map.hdb10.50 kB11-09-15|17:16
LCD.root_partition.map.kpt2.33 kB11-09-15|17:16
README653.00 B11-09-15|17:10
LCD.jdi135.00 B11-09-15|17:16
LCD.qpf1.26 kB11-09-15|17:09
LCD.qsf3.28 kB11-09-15|17:16
LCD.qws1.25 kB11-09-15|17:26
LCD.v1.47 kB11-09-15|17:19
LCD.v.bak1.42 kB11-09-15|17:10
LCD.asm.rpt7.71 kB11-09-15|17:16
LCD.done26.00 B11-09-15|17:17
LCD.fit.rpt214.06 kB11-09-15|17:16
LCD.fit.smsg703.00 B11-09-15|17:16
LCD.fit.summary609.00 B11-09-15|17:16
LCD.flow.rpt7.33 kB11-09-15|17:16
LCD.jdi332.00 B11-09-15|17:16
LCD.map.rpt29.32 kB11-09-15|17:16
LCD.map.smsg125.00 B11-09-15|17:16
LCD.map.summary460.00 B11-09-15|17:16
LCD.pin101.14 kB11-09-15|17:16
LCD.pof2.00 MB11-09-15|17:16
LCD.sof1.69 MB11-09-15|17:16
LCD.sta.rpt134.23 kB11-09-15|17:16
LCD.sta.summary1.05 kB11-09-15|17:16
compiled_partitions0.00 B11-09-15|17:16
db0.00 B11-09-15|17:26
incremental_db0.00 B11-09-15|17:10
output_files0.00 B11-09-15|17:16
LCD0.00 B11-09-15|17:26
...
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Verilog LCD code (414.39 kB)

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