Traffic_light
2016-08-23
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`timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:48:50 11/30/2015
// Design Name:
// Module Name: semaforo
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module semaforo(clk,rst,sR1,sA1,sV1,sR2,sA2,sV2);
output reg sR1,sA1,sV1,sR2,sA2,sV2;
input clk;
input rst;
&nbs
verilog
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