Beiyou digital experiment code
2017-12-27
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Experiment 1: design and implementation of Quartus Ⅱ schematic input method experiment 1: experimental requirements: ① design and implement a half adder with logic gate, simulate and verify its function, and generate a new half adder graphic module unit. &(2) a full adder is designed and implemented by using the half adder module and logic gate generated in Experiment 1. The function of the full adder is verified by simulation and downloaded to the experimental board for testing. The input signal is required to be set by the dial switch and the output signal is displayed by the LED. &Function f is designed and implemented with 3-wire-8-wire decoder and logic gate. The function is verified by simulation and downloaded to the experimental board for testing. The input signal is required to be set by dial switch, and the output signal is displayed by LED. 2: Report content
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