No self-introduction
Loading
Profile
Follow
codes (2)
LCD controller TFT
no vote
Application background Using FPGA control TFT LCD screen, using Verilog prepared FSM control TFT, control process includes a TFT initialization, clear screen, display pictures. The most important is to according to the specification TFT, written in the initialization process. Also note that the calculation of the location of the image display.
hxing 0 0
1
Controller SDRAM
no vote
Application background Controller RTL for the SDRAM level, by reading and writing state machine control, due to the SDRAM clock for verification of the maximum 133MHz, it uses 100MHz rate to write SDRAM, and then the SDRAM data into the FIFO, and then read from the FIFO data, displayed on the digital tube, FIFO is mainly used in the data cache, to avoid missing.
hxing 0 0
1
No more~
Follows0
Fans0