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lms speed 2
no vote
here i am uploading the lms algorithm spped 2 file in this we are using efficient fixed point implementation and area delay power efficient algorithm ..which is quite different than previous one..
majorproject
2018-08-13
0
1
c library
no vote
here i am uploading std library for c program s it con sist of all functions like printf and scanf ..not only printf and scanf there are many library functions are also there those will be very useful for any compiler this is having special some functions like sum and additions..
majorproject
2018-08-04
0
1
sine hexadecimal values
no vote
module DelayUnit(Clk,Reset,Enable,Data_in,Delay_out);     input    Clk,Reset,Enable;     input    [15:0] Data_in;     output    [15:0] Delay_out;       reg[15:0] Delay_out;       always @(posedge Clk or posedge Reset) begin         if (Reset ==1'b1) begin             Delay_out <= 0;         end         else begin             if (Enable == 1'b1) begin                 Delay_out <= Data_in;             end         end     end  <
majorproject
2018-07-01
0
1
verilog lms
no vote
`timescale 1ns / 10ps `define DATA_LEN 1024 // Length of Data Samples //`define DATA_LEN 2048 // Length of Data Samples `define COEFF_LEN 2 // Length of coefficients `define COEFF_MEM_WIDTH 10 // Coeff Memory width `define DATA_MEM_WIDTH 12 // Data Memory width //`include "div_gen_v2_0.v" module NLMS( RST, CLK, BUSY, Y_Bar, X_Bar, Xorg_Bar, ERROR ); input RST; //Reset input CLK; //Clock output BUSY; // Busy signal goes to one when NLMS is being performed output [15:0] Y_Bar; //output to the Test bench output [15:0] X_Bar; //output to the Test bench output [15:0] Xorg_Bar; //output to the Test bench output [15:0] ERROR; //error parameter [3:0] //state variable S1 = 4'b0000,
majorproject
2016-12-29
0
1
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