`timescale 1ns / 10ps
`define DATA_LEN 1024 // Length of Data Samples
//`define DATA_LEN 2048 // Length of Data Samples
`define COEFF_LEN 2 // Length of coefficients
`define COEFF_MEM_WIDTH 10 // Coeff Memory width
`define DATA_MEM_WIDTH 12 // Data Memory width
//`include "div_gen_v2_0.v"
module NLMS(
RST,
CLK,
BUSY,
Y_Bar,
X_Bar,
Xorg_Bar,
ERROR
);
input RST; //Reset
input CLK; //Clock
output BUSY; // Busy signal goes to one when NLMS is being performed
output [15:0] Y_Bar; //output to the Test bench
output [15:0] X_Bar; //output to the Test bench
output [15:0] Xorg_Bar; //output to the Test bench
output [15:0] ERROR; //error
parameter [3:0] //state variable
S1 = 4'b0000,