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generate gold code in simulink based vhdl
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library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
use work.clock_pkg.all;
entity xlclkprobe is
port (clk : in std_logic;
clr : in std_logic;
ce : in std_logic;
fakeOutForXst : out std_logic);
smankch14417170 2016-08-23
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