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half-adder
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it contain VHDL half -adder with test-bench test-bench means 'project maker can announce what time shall he give a term for example a <= '0', '1' after 5ns, '0' after 10ns, '1' after 15ns, '0' after 20ns, '1' after 25ns, '0' after 30ns, '1' 35ns; b <= '0', '1' after 10ns , '0' after 20ns, '1' after 30ns, '0' after 40ns;
shaku441268 0 0
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half-adder
no vote
it contains half-adder vhdl code and simulate form also, there is test bench coding for half-adder, which means writers can gave a clock by himself. like a <= '0', '1' after 5ns, '0' after 10ns, '1' after 15ns, '0' after 20ns, '1'after 25ns, '0' after 30ns, '1' after 35ns; b <= '0', '1' after 10ns, '0' after 20ns, '1' after 30ns, '0' after 40ns;
shaku441268 0 0
1
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