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A Robust Video Watermarking Algorithm for Content
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A novel video watermarking scheme is based on subband selection using discrete wavelet transform and singular value decomposition. To increase the level of authentication,
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verilog code for vedic multiplier
4.1
This is the source code for 8x8 vedic multiplier is designed by ancient vedic mathematics. It contains 16 sutra in that urdhva tiryagbhyam suytra is used. For the addition operation full adder is used .
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FPGA Implementation of high speed 8-bit Vedic mult
4.0
This paper describes the implementation of an 8-bit Vedic multiplier enhanced in terms of propagation delay when
compared with conventional multiplier like array multiplier, Braun multiplier, modified booth multiplier and Wallace
tree multiplier
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DESIGN OF 4 BIT CARRY-LOOK AHEAD ADDER
4.0
In this paper describes design of 4 bit carry-look ahead adder.this adder is high speed comparing to ripple carry adder.
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DESIGN OF 32 BIT CARRY-LOOK AHEAD ADDER
4.0
In this paper design of 32 bit carry look ahead adder is done .the complexity is reduced by designing 8 4 bit cla block.
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DESIGN OF 2X2 BIT VEDIC MULTIPLIER
4.0
IN THIS PROJECT ANCIENT VEDIC MATHEMATICS IS USED FOR THE MULTIPLICATION OPERATION.THE MULTIPLIER MAINLY USED IN DIGITAL SIGNAL PROCESSORS,CRYPTOGRAPHIC ALGORITHM. URTHVA TRIYAGBHYAM SUTRA IS USED FOR IMPLEMENTATION. UT IS SAID TO BE VERTICAL AND CROSSWISE MULTIPLICATION.
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